Detectors used in industrial automation are becoming smarter due to advancement in technology. For example, field devices used in industrial automation can communicate process variables using a current loop, and a controller can sense the current and interpret the process variable. When an analog signal is used, only one process variable can be transmitted. However, a digital signal can communicate information using frequency shift keying superimposed on an analog signal, thus increasing the number of process variables that can be sent to a controller using an existing analog signal line.
Most of detectors known in the art support standard protocols recommended by the industry, but these protocols pose a constraint on the manufacturer of the detector. For example, the manufacturer must use sophisticated chips to implement the standard protocols recommended by the industry, and these sophisticated chips can add to the overall cost of the detector. Furthermore, the protocols must comply with a set of physical layer specifications so that the digital communication superimposed on the analog line does not disturb the overall network of field devices and/or the controller.
HART (Highway Addressable Remote Transducer) protocol is one example of a widely accepted and implemented communication protocol that is commonly used in the instrumentation and process control industry. The HART protocol is used to communicate digital data and uses an FSK (Frequency Shift Keying) signal of 1200 Hz and 2200 Hz traveling on a conventional 4-20 mA current loop.
Devices that communicate via the HART protocol must decode and generate FSK signals. Therefore, the integration and implementation of HART capability in these devices is essential. However, modern circuitry that implements and is compliant with the HART protocol can be very expensive, especially in the demodulation section of the modem.
Various techniques have been tried to reduce the cost of the HART modem. For example, some techniques have employed a dedicated HART modem IC. Other techniques and approaches for decoding FSK signals have been software-based and FPGA/CPLD-based. However, each of these known techniques presents drawback and disadvantages.
One previously proposed technique is disclosed in Application Note 2336 titled “Simplified FSK Detection” (“AN 2336”). AN 2336 discloses a technique for and implementation of a dedicated HART modem IC in a PSoC® platform, and FIG. 1 is a block diagram of a demodulator as disclosed in AN2336. The technique and implementation disclosed in AN2336 and shown in FIG. 1 is both CPU-intensive and costly. For example, if implemented with microcontroller software, such a technique can utilize most CPU processing power. Furthermore, the comparator circuit, as seen in FIG. 1, can add to the overall cost of the demodulator.
Another previously proposed technique is disclosed in U.S. Publication No. 2009/0168857 titled “Micro-Controller With FSK Modem” (“the '857 publication”). The technique disclosed in the '857 publication is primarily based on counting the number of zero crossing instances in a given time period, and FIG. 2 is a block diagram of the method disclosed in the '857 publication. One of the drawbacks of the technique and implementation disclosed in the '857 publication is that they are CPU-intensive.
Yet another previously proposed technique is the A5191HRTL HART modem IC manufactured by ON Semiconductor. The A5191HRTL HART modem IC has been widely used in the industry to add HART capability to products, and FIG. 3 is a circuit block diagram of the implemented IC. As seen in FIG. 3, the implementation of this technique requires the use of an A5191 IC and various other discrete components. Accordingly, this technique and implementation is extremely costly.
In view of the above, there is a continuing, ongoing need for an improved apparatus and method for demodulation of FSK signals.